When a controller connected to NAND flash memory (hereinafter referred to as NAND) outputs a read enable signal to the NAND, the NAND inputs to the controller a data signal and a data strobe signal, which are in synchronism with the read enable signal. The controller latches the data signal by using a read clock signal formed by delaying the data strobe signal. With increase in speed of an interface of the NAND, the compression ratio of the data strobe signal to Valid Window becomes high due to the influence of the duty variation of the read enable signal in the controller. The Valid Window affects a set-up time and hold time upon latching data by the controller. Therefore, the controller performs control for allowing the Valid Window to secure a proper range.